Architect Labs Unveils Redwood: The World’s First Fully AI-Designed AI Chip That Runs AI Models

Architect Labs, an AI research lab for custom silicon, led by Ebrahim Hussain and Aaditya Subedi, has announced that its AI System generated and fully verified end-to-end from a human-written specification, a production-worthy AI accelerator called Redwood.

With just two human architects providing the specifications, the AI system designed and fully verified the chip in under two weeks. It also co-designed the firmware and custom kernels and mapped modern AI models to the hardware. The resulting accelerator is currently running on an FPGA platform, performing inference on multi-billion-parameter models including Llama and Qwen.

Redwood represents a major milestone for the semiconductor industry: an AI system has autonomously designed a production-ready AI chip capable of running AI models. The approach creates a feedback loop between AI models and the hardware optimized to run them, potentially accelerating chip design beyond traditional development cycles.

Performance results also point beyond a proof of concept. Projected onto Samsung’s 8nm process, Redwood delivers 1.75× the throughput at 1.9× lower power than NVIDIA’s Jetson Orin Nano, translating to a 3.4× improvement in performance per watt on the same AI models.

Closing the Loop Between AI and Silicon.

Chip design can take years and hundreds of millions of dollars, while a shrinking pool of specialized talent has concentrated advanced semiconductor development among a handful of major companies. As a result, AI workloads are often adapted to hardware designed long before the latest models emerged.

Redwood takes a different approach by co-designing hardware and software from the start. Kernels, firmware, and RTL are developed and optimized together, allowing the chip to be tailored to AI workloads rather than forcing software to fit existing hardware.

This creates a continuous feedback loop in which improved AI models can inform better hardware designs, while more efficient hardware enables better AI performance, potentially accelerating both sides of the development cycle.

"Chips were designed by one or two engineers when I started in this business four decades ago. Since then, design complexity, time, and risk have grown exponentially. Even with every advance in EDA tools and technologies, a single chip program consumed multiple years and enormous engineering teams," said Sunil Shenoy, former Senior Vice President of Engineering at Intel. "Redwood is a genuine paradigm shift, and a concrete benchmark of the frontier of what is possible. Architect Labs is democratizing capabilities that were the exclusive domain of a few giants, at a speed I would not have believed possible. Their approach promises to take hardware back to the future." 

Inside Redwood: A Frontier AI Accelerator.

Redwood is an end-to-end AI inference platform designed for physical AI applications such as robots, drones, and edge devices that require real-time performance within tight power constraints.

At its core is a scalable mesh of matrix and vector compute engines connected by a purpose-built on-chip network. The full AI inference pipeline, including attention, KV caching, and on-the-fly quantization, runs directly on the chip without relying on a host processor.

The compute engines, network, firmware, and custom kernels were designed together and optimized as a unified system, allowing the hardware to closely match modern AI workloads. Redwood can also scale into larger data-center SoCs or operate as a standalone chiplet.

Key Statistics on Autonomous Redwood Design: 

• Autonomous design and verification: 100% of the RTL, UVM verification environments, formal verification, firmware, drivers, and custom compute kernels were generated end-to-end by Architect Labs' AI system from a human-written specification in under two weeks with two human architects working on the project. 

• Signoff-grade verification, zero hardware bugs: Every block, from individual IP to the full SoC, closed at over 95% code and functional coverage using commercial EDA tools, Architect Labs' proprietary formal engine, and hardware-in-the-loop validation. The first RTL drop from simulation to FPGA platform contained zero bugs. 

• Running real AI models on real hardware: Redwood Nano is deployed on an AMD Versal FPGA at 250 MHz, executing real-time, single-batch inference on open-weight models including Qwen. Architect Labs ran live hardware demos at this year's Design Automation Conference (DAC), one of the only companies at the show demonstrating an AI-designed accelerator running inference on models live.

• Outperforming today’s leading-edge AI silicon: Projected onto Samsung 8 nm, the same process class as NVIDIA's Jetson Orin Nano, Redwood delivers 1.75x the throughput at 1.9x lower power, a 3.4x improvement in performance per watt, against a measured Jetson baseline running the same model. These projections are calibrated from direct FPGA measurements, not simulation alone. 

• Architectural iteration in days, not quarters: Any change to the high-level specification results in fully regenerated, reverified, and redeployed hardware in under 48 hours, with the exception of SoC-level runs bounded by EDA tool runtimes. 

• Recursive self-improvement: An AI model deployed on Redwood exposed as an API endpoint, discovered timing and kernel optimizations for the accelerator itself, at near-zero inference cost, closing the loop of AI and the silicon that fuels it. 

"Every era of computing has been enabled by the underlying hardware, but also gated by who could afford to build the silicon for it," said Steve Jang, Founder and Managing Partner at Kindred Ventures. "The Redwood chip is early proof that the gate can come down: two people - starting with a written specification and target AI model - used Architect Labs' system to fully design, verify, and deploy a competitive AI accelerator in weeks. Whether you are a frontier research lab, robot maker, or a cloud operator, the concept of making your own custom silicon purpose-built for your product or platform is now becoming a reality." 

A Fundamentally New Way of Designing Software to Silicon.

Architect Labs’ AI system optimizes the entire computing stack, from models and kernels to firmware and RTL, in parallel, rather than through the sequential, siloed workflows common in traditional chip design. This allows software and silicon to be co-optimized through tape-out, with design iterations potentially taking weeks instead of months.

The approach can shift functions between software and hardware based on efficiency, for example, replacing thousands of software cycles with dedicated hardware logic or moving scheduling tasks to the compiler. Redwood demonstrates that these tradeoffs can now be designed, verified, and tested in hardware within days, providing a foundation for scaling the approach to more complex chips.

"Three decades ago, foundries like TSMC made world-class manufacturing available to anyone with a design, and the fabless industry with companies like NVIDIA, Broadcom, and Apple was born," said Ebrahim Hussain, co-founder and CEO of Architect Labs. "In a similar fashion, we are pioneering the designless semiconductor industry, where chips like Redwood are co-designed and co-evolved with the workloads they run. We envision that software companies with intensive workloads or specialized AI models can get co-designed custom silicon, without having to build a large design team, stake a decade on an architectural bet, or fall back to off-the-shelf general-purpose solutions, leaving performance, power, and cost savings on the table. Every workload that matters deserves its own custom chip. We are building towards a future where they can have one." 

Architect Labs is already applying the same approach with Fortune 500 partners, co-designing custom chip designs at the speed of software and compressing programs that would traditionally run for months into ones measured in weeks. Redwood is the first public demonstration of what that makes possible. 

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